View ML70512HB_6782432.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

oki semiconductor fedl70512-04 issue date: sep. 2, 2003 ml70512 bluetooth baseband controller ic 1/29 general description the ml70512 is a cmos digital ic for use in 2.4 ghz band bluetooth? systems. this ic incorporates the arm7tdmi ? as the cpu core, features a highly expandable arch itecture, and supports th e interfaces for a variety of applications. since the ml70512 has oki?s bluetooth protocol stack software installed, when the ic is used in conjunction with the bluetooth rf transceiver ic, data/voice communications are possible while maintaining interconnectivity with other bluetooth systems. features ? conforms to bluetooth specification (ver1.1) ? designed for connection w ith the rf-lsi interface, su ch as the oki rf-lsi inte rface (ml7050, ml70561), the skyworks rf-lsi interface (cx7230 3), or the broadcom rf-lsi inte rface (bcm2002x) that functions as the bluetooth rf-lsi interface ? the high-speed, low-power arm7tdmi tm is installed as the cpu core ? pcm-cvsd transcoder that provides high qua lity voice using the noise filter is installed ? low power consumption in flexible power management modes according to operating modes of bluetooth ? detach signal provides control of change to power-saving mode (stop) and return request to normal mode. ? uart interface corresponding to baud rates up to 921.6 kbps ? i 2 c bus interface provides acce sses to eeprom or pcm-codec ? selactable 12 mhz, 13 mhz, or 16 mhz for the system clock ? selectable 32 khz or 32 .768 khz for the lpo clock ? built-in programmed rom eliminates external rom/flash ? the packages are available in two types: 83-pin wcsp for ML70512HB 84-pin bga for ml70512la arm, arm7tdmi and thumb are re gistered trademarks of arm ltd., uk. bluetooth is a trademark owned by bluetooth sig, inc. and licensed to oki electric industry. the information contained herein can change without notice owing to the product being under development.
fedl70512-04 oki semiconductor ml70512 2/29 specifications process 0.16 p m cmos (5-layer metal wire) package 83-pin wcsp (p-vflga83-6.22 u 6.22-0.50-w) (dimensions: 6.22 mm u 6.22 mm u 0.48 mm; pin pitch: 0.50 mm) 84-pin bga (p-lfbga84-0909-0.80) (dimensions: 9 mm u 9 mm u 1.5 mm; pin pitch: 0.80 mm) supply current 23.4 ma (24 mhz operation) operating voltage ranges 2.70 to 3.6 v for input-output, 1.65 to 1.95 v for internal circuits operating frequency 24 mhz built-in rom size 384 kb (for arm program) built-in ram size 72 kb input clocks 12 mhz, 13 mhz, or 16 mhz (system clock) 32 khz or 32.768 khz (lpo clock) rf-lsi interface oki rf-lsi interface (ml7050, ml70561) skyworks rf-lsi interface (cx72303 ) broadcom rf-lsi interface (bcm2002x) installed interfaces uart interface (up to 921.6 kbps) general-purpose i/o interface (bits 0 and 1 are used as a pin for i 2 c bus interface depending on software installed) pcm interface (pcm linear/a-law/ p -law can be selected) detach interface timers 16-bit auto reload timer (1ch) 18-bit auto reload timer (3ch) interrupt controller 11 causes clock control circuit crystal oscillator circuit (12 mhz, 13 mhz, or 16 mhz, 32 khz or 32.768 khz) internal pll
fedl70512-04 oki semiconductor ml70512 3/29 pin placement ML70512HB: 83-pin wcsp (p-vflga83-6.22 u 6.22-0.50-w) sclko top view sfrq sel1 core vdd gnd cio6 cio3 1 2 3 4 5 6 7 8 a b c d e f g h j k gnd gnd pcm out core vdd pcm clk pcm sync cio5 core vdd cio0 ( scl ) cio1 (sda) cio4 9 10 rfsel0 rts rfsel2 gnd gnd core vdd gnd gnd sin sout pll_ clk vdd pll_ data pll_ pow pll_ off tx_ pow rx_ pow pll_le rxd pll_ps txd gnd rssi core vdd gnd vdd sfrq sel0 vdd vdd xc32kn sclk sel xc32kp gnd detach vdd sclkp agnd0 agnd1 agnd0 core vdd avdd0 avdd1 core vdd agnd1 gnd gnd gnd pcmin vdd cio2 rfsel1 core vdd vdd cts lvdd avdd0 rssi _clk avdd1 pll lock core vdd gnd gnd gnd sclkn gnd reset
fedl70512-04 oki semiconductor ml70512 4/29 ml0512la: 84-pin bga (p-tfbga84-0909-0.80) top view pll_ps pll_ data gnd sfrq sel0 gnd core vdd vdd rxd gnd xc32kn 1 2 3 4 5 6 7 8 a b c d e f g h j k xc32kp gnd avdd1 agnd1 agnd1 agnd0 avdd0 gnd agnd0 vdd gnd cio4 9 10 cts core vdd rfsel2 avdd1 reset rfsel0 sclkn vdd pll lock gnd txd pll_le tx_ pow pll_ pow rx_ pow pll_ off gnd rssi_ clk pll_ clk lvdd vdd sout sfrq sel1 sin gnd core vdd cio3 gnd gnd vdd rts gnd cio2 cio1 ( sda ) vdd gnd pcm out gnd core vdd pcm sync nc gnd core vdd gnd sclk sel avdd0 core vdd sclkp detach rfsel1 vdd cio5 rssi pcmin pcmclk vdd nc cio6 core vdd sclko core vdd cio0 (scl)
fedl70512-04 oki semiconductor ml70512 5/29 pin descriptions rf i/f pin placement pin name direc- tion [*0] internal pull up/ down, schmitt initial value ML70512HB ml70512la description txd o ? l l l l c1 a4 ml7050: transmit data output cx72303: transmit data output bcm2002x: transmit data output ml70561: transmit data output rxd i ? ? ? ? ? d1 a5 ml7050: receive data input cx72303: receive data input bcm2002x: receive data input ml70561: receive data input pll_data o ? x h l l a3 c3 ml7050: serial write data cx72303: serial write data bcm2002x: transmit enable ml70561: transmit enable (active h) pll_clk o ? l l l l b4 c1 ml7050: serial clock cx72303: serial clock bcm2002x: serial clock ml70561: serial clock l h l pll_le o ? l b1 a3 ml7050: serial road enable 0: negate, 1: assert cx72303: serial enable 0: assert, 1: negate bcm2002x: rf-lsi synthesizer on 0: negate, 1: assert ml70561: rf-lsi synthesizer on 0: negate, 1: assert rssi i ? ? ? ? ? e2 c5 ml7050: receive fi eld strength data input cx72303: serial read data bcm2002x: serial read data ml70561: serial read data rssi_clk o ? h l h h c4 c2 ml7050: receive fi eld strength data clock cx72303: rf-lsi receiving characteristic control bcm2002x: system clock request ml70561: system clock request pll_pow o ? h l h h b3 a1 ml7050: local pll power control 0: assert, 1: negate cx72303: pa power control 0: negate, 1: assert bcm2002x: select serial transmit mode ml70561: select serial transmit mode
fedl70512-04 oki semiconductor ml70512 6/29 pin placement pin name direc- tion [*0] internal pull up/ down, schmitt initial value ML70512HB ml70512la description tx_pow o ? h l l l a1 a2 ml7050: transmit enable 0: assert, 1: negate cx72303: transmit enable 0: negate, 1: assert bcm2002x: serial write data ml70561: serial write data rx_pow o ? h l l l b2 b2 ml7050: receive enable 0: assert, 1: negate cx72303: receive enable 0: negate, 1: assert bcm2002x: receive enable ml70561: receive enable [*0] ?i? = input, ?o? = output, ?i/o? = input/output
fedl70512-04 oki semiconductor ml70512 7/29 rf i/f pin placement pin name direc- tion [*0] internal pull up/ down, schmitt initial value ml70512h b ml70512la description pll_ps o ? l l l l c2 b3 ml7050: ?l? cx72303: power on reset 0: assert (reset) 1: negate bcm2002x: rf-lsi receiving characteristic control ml70561: syncword detection plllock i ? ? ? ? ? h3 b5 ml7050: ? cx72303: ? bcm2002x: 1mhz clock ml70561: clock for 1 mhz transmit data h ? l pll_off o ? l a2 b1 ml7050: pll loop control 0: open loop 1: closed loop cx72303: diversity output bcm2002x: pa power control ml70561: pa power control clk and configuration pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description sclkp i ? ? k6 f8 sclkn o ? ? j7 f10 system clock (12/13/16 mhz) pins (power level: cmos level) xc32kp i ? ? k1 a9 xc32kn o ? ? h1 b8 subclock pins (for oscillator) sclksel i ? ? j1 c8 system clock frequency select pin l: select clk divided by internal pll h: select subclock sfrqsel 0?1 i ? ? *[1] *[2] system clock (sclk) frequency select/ bcm crystal frequency select pins rfsel 0?2 i ? ? *[3] *[4] rf-lsi select pins sfrqsel [1:0] sclk input frequency (rfsel z 101) bcm crystal frequency (rfsel = 101) 00 13 mhz 19.68 mhz 01 12 mhz 19.2 mhz 10 16 mhz 19.8 mhz 11 reserved 13 mhz rfsel[2:0] rf-lsi 001 ml7050 (oki) 010 cx72303 (skyworks) 011 ml70561 (oki) 101 bcm2002x (brosdcom) others reserved
fedl70512-04 oki semiconductor ml70512 8/29 clk and configuration pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description reset i schmitt ? k8 g10 hardware reset pin (reset = l) detach i schmitt ? j8 g8 sleep pin (sleep = l) sclko o ? ? b10 h3 system clock (12/13/16 mhz) output pins [*1] sfrqsel0: g2; sfrqsel1: a6 [*2] sfrqsel0: c7; sfrqsel1: f2 [*3] rfsel0: j9; rfsel1: h8; rfsel2: k10 [*4] rfsel0: h10; rfsel1: h8; rfsel2: k10 pcm i/f pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description pcmout o ? l c9 j4 pcm data output pcmin i pull up ? e8 h5 pcm data input pcmsync i/o pull down ? d10 k4 pcm sync signal (8 khz), initial setting: input (can be switched by an internal register) pcmclk i/o pull down ? d9 h4 pcm clock (64 khz/128 khz) initial setting: input (can be switched by an internal register) note: the pcm sync signal (8 khz) mu st be guaranteed at the accuracy of r 50 ppm if the pcmsync pin is configured as an input. uart i/f pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description sout o ? h b5 e1 ace transmit serial data sin i schmitt ? b7 f1 ac e receive serial data rts o ? ? j10 k9 ace transmit data ready cts i ? h h6 j9 ace transmit ready
fedl70512-04 oki semiconductor ml70512 9/29 port pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description cio0 (scl) i/o ? h f9 h7 i 2 c serial clock (output) cio1 (sda) i/o ? ? g9 k7 i 2 c serial data (input) cio2 i/o ? ? g8 k8 general por t (initial state: input) cio3 i/o ? l b8 h2 general port (initial state: output) cio4 i/o ? h h9 h9 general port (initial state: output) cio5 i/o ? ? e9 h6 general por t (initial state: input) cio6 i/o ? ? b6 f3 general por t (initial state: input) nc pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description nc ? ? ? ? [*4] no connection [*4] nc: e3, j3 note: do not wire under the nc pin.
fedl70512-04 oki semiconductor ml70512 10/29 power, gnd pin placement pin name direc- tion internal pull up/ down, schmitt initial value ML70512HB ml70512la description v dd ? ? ? [*5] [*6] i/o power supply pin 2.70 to 3.6 v corev dd ? ? ? [*7] [*8] power supply pin for internal circuit 1.65 to 1.95 v lv dd ? ? ? c5 d2 rf-i/o power suply pin (same voltage to the v dd for rf-lsi) gnd ? ? ? [*9] [*10] digital block ground pin av dd 0 ? ? ? [*11] [*12] av dd 1 ? ? ? [*13] [*14] analog block power supply pin 1.65 to 1.95 v agnd0 ? ? ? [*15] [*16] agnd1 ? ? ? [*17] [*18] analog block ground pin [*5] v dd : a4, c6, f1, f8, g1, h2, k7 [*6] v dd : a8, b7, c6, d3, e2, f9, k1, k6 [*7] core v dd : a8, c7, c10, d3, e1, e10, g10, k2, k5 [*8] core v dd : a6, e8, g1, g3, j7, j10, k3, k5 [*9] gnd: a5, a7, a9, a10, b9, c8, d2, d8, e3, f2, f3, f10, g3, h7, h10, j2, k9 [*10] gnd: a7, a10, b4, b6, c4, d1, e9 , g2, g9, h1, j1, j2, j5, j6, j8, k2 [*11] av dd 0: h5, k4 [*12] av dd 0: d8, d10 [*13] av dd 1: h4, j3 [*14] av dd 1: b9, b10 [*15] agnd0: j5, j6 [*16] agnd0: d9, e10 [*17] agnd1: j4, k3 [*18] agnd1: c9, c10
fedl70512-04 oki semiconductor ml70512 11/29 block diagram default slave timer2 (3ch) detach if 72kb ram default slave arm7 tdmi amba ahb amba apb tic arbiter ahb ctl system control 384kb rom amba apb ctl/ wdt i/f gpio i/f irc apb ctl timer gpio i/f clk gen cloc k ml70512 uart i/f uart i/f iramc iromc processor bus apb ctl i/f pcm/ cvsd i/f i/f bt-bb core i/f i/f detach i/f pcm codec rflsi
fedl70512-04 oki semiconductor ml70512 12/29 description of internal blocks clkgen block ? generates a clock that is supplied to each block through sclkp (12/13/16 mhz) ? stop/halt function ctl/wdt block ? control of the frequency division function of the internal main clock ? control of clock supplied to each peripheral ? control of reset of each peripheral ? stop/halt control ? watchdog timer function (interrupt/reset) timer block ? 3 channels ? 18-bit timer counter ? interrupt by compare function ? one shot, interval, or free-run mode base band core block ? rf controller - rf power supply control (pll, tx, rx) - local pll frequency division ratio setting - receive clock re generation function - synchronization detection (synchronizing within the permissable error limit of syncword) - receive clock re-timing function ? fh controller hopping - sequence control - frequency hopping selection function - crc computation's initial value selection function packet decomposer fhcnt rf cnt packet composer rf lsi tx sco buffer timing codec i/f arm i/f rxd txd audio apb tx acl buffer rx sco buffer rx acl buffer security cnt
fedl70512-04 oki semiconductor ml70512 13/29 ? timing generator - bluetooth clock generation - operation interrupts depend on mode (slot, scan, sniff, hold, park) - sync detection timing generation (sync window 10 p s) - pll setting timing generation - transmit/receive timing generation - multi-master timing management function ? packet composer - access code generation (syncword generation, appending pr*trailer) - packet header generation (hec generation, scrambling, fec encoding) - payload generation (crc generation, encryption, scrambling, fec encoding) - packet synthesis ? packet decomposer - packet decomposition (separating the packet header and the payload) - packet header processing (fec decoding, descrambling, hec error detection, header information separation) - payload processing (fec decoding, descrambling, encryption decoding, crc judgement, payload separation) ? security - various key generation functions (initialization, link key, encryption key) - certification function - encryption function
fedl70512-04 oki semiconductor ml70512 14/29 uart block ? full-duplex buffering method ? all status reporting function ? built-in 64-byte tr ansmit/receive fifo ? modem control based on cts ? programmable serial interface ? 5-, 6-, 7-, 8-bit characters ? generation and verification of odd parity, even parity, or no parity ? 1, 1.5, or 2 stop bits ? programmable baud rate generator (9600 bps to 921.6 kbps) ? error servicing for parity, overrun, and framing errors ? configuration of 1 data frame during reception ? configuration of 1 data frame during transmission sin sample clk 5 data bits to 8 data bits parity stop start sout start 5 data bits to 8 data bits parity stop
fedl70512-04 oki semiconductor ml70512 15/29 pcm-cvsd transcoder block ? application side i/o: - pcm codec ? application-side format: - pcm linear (8, 14, 16 bits/sample, 8 khz sampling frequency)/a-law/ p -law ? bluetooth-side format: - cvsd/a-law/ p -law ? all combinations of the above conversions are supported ? pcmsync/pcmclk i/o can be switched (initial setting: input) ? timing in short mode and in pcmclk and pcmsync output mode (for pcm data of 14 bits/sample, lo wer 2 bits of 16 bits are invalid.) ? timing in short mode and in pcmclk and pcmsync input mode. (for pcm data of 14 bits/sample, lo wer 2 bits of 16 bits are invalid.) 125 p s (8khz) pcmclk(i) 64k/128khz pcmsync(i) 8 bits or 16 bits pcmclk(o) 64k/128khz pcmsync(o) lsb msb data data data lsb data msb data is output on the rising edge of clk. pcmout lsb msb data data data lsb data msb pcmin data is shifted in on the falling edge of clk 125 p s (8khz) 8 bits or 16 bits lsb msb data data data lsb data msb data is output on the rising edge of clk. pcmout lsb msb data data data lsb data msb pcmin data is shifted in on the falling edge of clk
fedl70512-04 oki semiconductor ml70512 16/29 ? timing in long mode and in pcmclk and pcmsync output mode (for pcm data of 14 bits/sample, lo wer 2 bits of 16 bits are invalid.) ? timing in long mode and in pcmclk and pcmsync input mode. (for pcm data of 14 bits/sample, lo wer 2 bits of 16 bits are invalid.) detach interface block ? generation of the request for change to (from) the st op mode by detection of the rising (falling) edge of the detach signal ? generation of the request for restore from the stop mode by detection of a sin signal level change msb data data data data lsb data msb 8 bits or 16 bits data is output on the rising edge of clk. pcmclk(i) 64k/128khz pcmout msb data data data data lsb data msb pcmin data is shifted in on the falling edge of clk. t pcmclk p eriod ( min. ) or d 62.5 p s ( max. ) 125 p s (8khz) msb data data data data lsb data msb 8 bits or 16 bits data is output on the rising edge of clk pcmclk(o) 64k/128khz pcmsync(o) pcmout msb data data data data lsb data msb pcmin data is shifted in on the falling edge of clk pcmclk p eriod u 3 125 p s (8khz)
fedl70512-04 oki semiconductor ml70512 17/29 absolute maximum ratings parameter symbol conditions rating unit i/o power supply voltage v dd /lv dd ? ?0.3 to +4.5 v core power supply voltage corev dd /av dd ? ?0.3 to +2.5 v input voltage v i ? ?0.3 to +4.5 v allowable power dissipation p d ? 0.62 w storage temperature t stg ? ?55 to 150 c recommended operating conditions parameter symbol conditions min. typ. max. unit i/o power supply voltage v dd /lv dd ? 2.7 3.3 3.6 v core power supply voltage corev dd /av dd ? 1.65 1.8 1.95 v ?h? level input voltage vih ? 2.2 ? v dd v ?l? level input voltage vil ? 0 ? 0.8 v operating temperature ta ? ?40 ? 85 c electrical characteristics dc characteristics (v dd = 2.7 to 3.6 v, corev dd = 1.65 to 1.95 v, ta = ?40 to +85c) parameter symbol conditions min. typ. max. unit 3.0v d vdd d 3.6v 2.4 ? ? ?h? level output voltage voh ioh = ?2 ma 2.7v d vdd 3.0v 2.2 ? ? v ?l? level output voltage vol iol = 2 ma ? ? 0.4 v vi = gnd to 3.6 v ?10 ? 10 vi = v dd 50 k : pull-down 10 66 200 input leakage current ii vi = gnd 50 k : pull-up ?200 ?66 ?10 p a vo = gnd to v dd ?10 ? 10 output leakage current io vo = v dd 50 k : pull-down 10 66 200 p a power supply current (during operation) iddo during 24 mhz operation 0 23.4 33 ma power supply current (during stand-by) idds clk stopped ? 50 250 p a
fedl70512-04 oki semiconductor ml70512 18/29 power supply current (iddo) charac teristics by power saving mode (v dd = 2.7 v to 3.6v, corev dd = 1.65 v to 1.95v, ta = -40 to 85c) operating mode conditions min. typ. max. unit stop mode ( detach = "l") ? ? 0.05 ? page scan operating mode interval:1.28sec window:22.5msec ? 1.5 ? poll interval operating mod interval:40slot ? 12.1 ? sniff operating mode interval:2000slot attempt:4frame ? 1.7 ? hold operating mode interval:4000slot ? 4.9 ? dh1/dm1 ? 23.4 ? rx:dh3/dm3 tx:dh1/dm1 ? 20.5 ? acl operating mode rx:dh5/dm5 tx:dh1/dm1 ? 19.6 ? ma ac characteristics ~ system clock (sclkp) (v dd = 2.7 to 3.6v, corev dd = 1.65 to 1.95v, ta = -40 to 85c) parameter description min typ max unit tmc0 duty in sclkp ?h? duration 40 50 60 % tmc1 duty in sclkp ?l? duration 40 50 60 % ~ sub-clock (xc32kp) (v dd = 2.7 to 3.6v, corev dd = 1.65 to 1.95v, ta = -40 to 85c) parameter description min typ max unit tmp0 duty in xc32kp ?h? duration 40 50 60 % tmp1 duty in xc32kp ?l? duration 40 50 60 % sclkp tmc0 tmc1 xc32kp tmp0 tmp1
fedl70512-04 oki semiconductor ml70512 19/29 ~ reset (v dd = 2.7 to 3.6v, corev dd = 1.65 to 1.95v, ta = -40 to 85c) parameter description min typ max unit t resw reset pulse width 10 ? ? p s note : apply "l" to the reset pin for 10 p sec or more after the power supply has been settled. v dd /lv dd rese t power supply stable period t resw corev dd /av dd
fedl70512-04 oki semiconductor ml70512 20/29 ~ pcm interface (vdd = 2.7 to 3.6v, corevdd = 1.65 to 1.95v, ta = -40 to 85c) parameter description min typ max unit tpc0 pcmin setup time relative to pcmclk (input) falling edge 100 ? ? ns tpc1 pcmin hold time relative to pcmclk (input) falling edge 100 ? ? ns tpc2 pcmout delay time relative to pcmclk (input) rising edge ? ? 250 ns tpc3 pcmsync (input) setup time re lative to pcmclk (input) rising edge 100 ? ? ns tpc4 pcmsync (input) hold time relative to pcmclk (input) rising edge 100 ? ? ns tpc5 pcmin setup time relative to pcmclk (output) falling edge 100 ? ? ns tpc6 pcmin hold time relative to pcmclk (output) falling edge 100 ? ? ns tpc7 pcmout delay time relative to pcmclk (output) rising edge ? ? 250 ns tpc8 delay time from pcmclk (output) rising edge to pcmsync (output) ? ? 150 ns ~ ac characteristic measuring points v dd 0 v 0.8v dd 0.2v dd 0.8v dd 0.2v dd pcmclk(i) pcmin pcmout tpc2 tpc2 tpc0 tpc1 pcmsync(i) tpc3 tpc4 tpc3 tpc4 pcmclk(o) pcmin pcmout tpc5 tpc6 pcmsync(o) tpc 8 tpc7 tpc 7
fedl70512-04 oki semiconductor ml70512 21/29 reference for voltage supply circuit ? insert appropriate bypass capacitors between the v dd and gnd lines. note 1: precautions to insert the bypass capacitors - use traces of v dd and gnd lines wider than those of the other signal lines. - keep the length of traces betw een the bypass capacitors and the v dd line and between the bypass capacitors and the gnd line as short as possible. - keep the length of traces betwee n the bypass capacitors and the v dd line and between the bypass capacitors and the gnd line as equal as possible. the circuit is subject to change accord ing to the specific lsi board design. pl ease contact oki elect ric industry co., ltd. for detailed information. feed lines should be separated from lsi pins. example of ml70512 voltage supply circuit capacitors should locate close to lsi pins. gnd vdd corevdd ml70512 avdd0 agnd0 avdd1 agnd1 0.1 p f 10 to 47 p f 0.1 p f 0.1 p f corevdd 0.1 p f 0.1 p f 0.1 p f vdd gnd 10 to 47 p f 10 to 47 p f 0.1 p f 0.1 p f lvdd
fedl70512-04 oki semiconductor ml70512 22/29 reference for oscillator ciucuit note 1: the values of c0 and c1, and r0 and r1 should be determined according to the specifications for the external crystal x?tal 1 (32 or 32.768 khz). the values of c2 and c3, and r2 and r3 should be determined according to the specifications for the external crystal x?tal 2 (12, 13, or 16 mhz). note 2: the crystal oscillator circuit should be connect ed to pins sclkp and sclkn only when the oki rf-lsi (ml7050) is connected. in other cases, the system clock should be input from the rf-lsi to pin sclkp. note 3: in the case of 12 mhz, 13 mhz, or 16 mhz system clock (sclkp) input, make sure the crystal frequency tolerance is 20 ppm for temperature, supply voltage, and aging. in the case of 32 khz or 32.768 khz sub-clock (xc32k p) input, make sure the crystal frequency tolerance is 250 ppm for temperature, supply voltage, and aging. note 4: precautions to build a crystal oscillator circuit - keep length of wire traces as short as possible. - do not cross the crystal oscillator circuit wires over other signal line wires. - do not keep signal line wires through which high cu rrent flows close to the crystal oscillator circuit. - keep the grounding point of the capacitors in the oscillator circuit at the potential equal to gnd. and do not connect the capacitors to the gnd or gn d lines through which high current flows. - do not output signals from the oscillator circuit. the circuit is subject to change accord ing to the specific lsi board design. pl ease contact oki elect ric industry co., ltd. for detailed information. it is recommended to determine the final circuit values including the capacitance of the circuit board designed by the user. ml70512 xc32kp xc32kn c1 c0 r0 x?tal 1 r1 sclkp sclkn c3 c2 r2 x?tal 2 r3 example of oscillator circuit connect this oscillator circuit only when connecting the oki rf-lsi ml7050.
fedl70512-04 oki semiconductor ml70512 23/29 application notes clock selection ? the system clock frequency is selected according to external pin sfrqsel. sfrqsel = 00 : a 13 mhz clock is input to external pin sclkp. sfrqsel = 01 : a 12 mhz clock is input to external pin sclkp. sfrqsel = 10 : a 16 mhz clock is input to external pin sclkp. a 12 mhz clock is input to external pin sclkp regardless of sfrqsel when bcm2002x is selected (rfsel = 101). ? the cpu clock supply source is selected according to external pin sclksel. sclksel = 0 : use the clock that was divided down from the internal pll output of 192 mhz that was generated from external pins sclkp. (dividing ratios are selectable in the range of 1/6 to 1/16. initial value is 1/8 (24 mhz).) sclksel = 1 : use external pins xc32kp. note: the clock supply source can be set by the clkcntl register in the ctl/wdt block once the lsi is powered up. ? the frequency of cpu clock is selectable from the high speed (24 mhz) and low speed (16 mhz). this can be performed by the vendor specific command. setting the reset ? apply ?l? level to the reset pin for more than 10 p s after power voltage is stabilized. when the system clock oscillator circuit is stable and the reset pin is at ?h? level, the internal reset is released and operation starts after the internal reset is held for 1.9 ms for the input clock of 13 mhz, 2.0 ms for the input clock of 12 mhz, or 1.5 ms for the input clock of 16 mhz. moreover, after power voltage is stable, the valu es of sclksel, sfrqsel0-1, and rfsel0-2 should be determined before the reset pin is at ?h? level. setting the uart baud rate ? it is possible to set the uart baud rate using the vendor specific commands. available baud rate settings: 9600/19.2k/38.4k/56k/57.6k/115.2k/230.4k/345.6k/460.8k/921.6k (initial value is 115.2 kbps.) setting the pcm-cvsd transcoder ? it is possible to set the pcm-cvsd tran scoders using the vendo r specific commands. for command details, contact oki electric industry co., ltd.
fedl70512-04 oki semiconductor ml70512 24/29 ? it is possible to set the following parameters using the vcctl command: - pcmsync/pcmclk mode (initial setting: input) - mute reception (initial setting: off) - mute transmission (initial setting: off) - aircoding cvsd (initial setting)/ p -law/a-law - interface coding linear (initial setting)/ p -law/a-law - pcm format (data width of one pcm linear sample) 8-bit (initial setting)/14-bit/16-bit - serial interface format short frame (initial setting)/long frame - application interface mode pcm codec i/f (initial setting)/apb i/f xtal input frequency of bcm2002x ? if the system clock is supplied from bcm2002x, the xtal input frequency of bcm2002x must be 13, 19.2, 19.68, or 19.8 mhz. 12 mhz should not be applied. xtal input frequency of cx72303 ? if the system clock is supplied from cx72303, the xtal input frequency of cx72303 must be 13 mhz. 10 mhz should not be applied. required processes when in terface pins are unused ? the following tables show the processes that should be performed when interface pins are not used. ? the pins that are not included in the following table should be left open. rf i/f pin name process when pin not used comments rxd gnd rssi gnd plllock gnd uart i/f pin name process when pin not used comments sin v dd cts gnd pcm i/f pin name process when pin not used comments pcmin open or v dd pcmsync open or gnd pcmclk open or gnd processes of other pins test i/f etc. pin name process when pin not used comments detach pull up or v dd
fedl70512-04 oki semiconductor ml70512 25/29 ml7050 vdd vdd msm7702-01 pcmout pcmin rsync bclk xsync vdd_d rxd pll_le pll_data pll_clk pll_off txd pll_pow rx_pow tx_pow mclk ant reset pcmout pcmin pcmsync pcmclk sclksel sfrqsel0 rfsel2 rfsel1 rfsel0 detach avdd0 agnd0 avdd1 agnd1 corevdd vdd gnd nc rxd pll_le pll_data pll_clk pll_off txd pll_pow rx_pow tx_pow rssi rssi_clk pll_ps plllock sclko sclkn sclkp xc32kn xc32kp sout rts sin cts cio6 cio5 cio4(led1) cio3(led0) cio2 sda(cio1) scl(cio0) rfvdd vdd corevdd gnd gnd gnd gnd gnd dsub9pin uart i/f 4 5 6 7 8 9 1 2 3 td rd rts cts gnd sda scl vcc gnd vdd vdd vdd at24c02 gnd gnd t1in t2in t3in r1out r2out t1out t2out r1in r2in gnd vdd max3245 vdd ml70512 lvdd vdd gnd gnd gnd gnd sfrqsel1 gnd the capacitors should be as close to the lsi pins as possible. separate, as far as possible, the wiring from the board pins. microphone speaker voice input/ output peripherals poewr on reset hardware reset ml70512/ml7050 system configuration example 68k : 68k : 47k : 13mhz 20ppm 32.768khz 250ppm 32khz or 0.1 p 0.1 p 0.1 p 0.1 p 47 p 0.1 p 0.1 p 47 p 0.1 p 0.1 p 47 p
fedl70512-04 oki semiconductor ml70512 26/29 package dimensions ML70512HB - 83pinwcsp (p-vflga83-6.22 u 6.22-0.50-w) p-vflga83-6.22 6.22-0.50-w package material epoxy resin lead frame material sn/pb pin treatment solder plating ( 5m) package weight (g) 0.04 typ. 5 rev. no./last revised 1/july 5, 2002 note: a lead-free package is available. please contact oki sales office/distributors for more information. notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humi dity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl70512-04 oki semiconductor ml70512 27/29 p-lfbga84-0909-0.80 package material epoxy resin ball material sn/pb package weight (g) 0.20 typ. 5 rev. no./last revised 1/may 15, 2000 (unit: mm) ml70512la - 84pin bga (p-lfbga84-0909-0.80) note: a lead-free package is available. please contact oki sales office/distributors for more information. notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humi dity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl70512-04 oki semiconductor ml70512 28/29 revision history page document no. date previous edition current edition description fedl70512-01 feb. 17, 2003 ?- ?- final edition 1 ?- ?- final edition 2 fedl70512-02 mar. 18, 2003 23 23 eliminated the ? reset ? row in the table of the ?test i/f ? section. ?- ?- final edition 3 fedl70512-03 apr. 8, 2003 18 18 partially eliminated t he contents of ?reset? section. 2 2 partially eliminated the contents of ?specifications? section. 17 17 partially eliminated the contents of ?dc characteristics? section. 18 18 partially eliminated t he contents of ?power supply current (iddo) characteristics by power saving mode? section. fedl70512-04 sep. 2, 2003 23 23 partially eliminated the contents of ?setting the reset? section.
fedl70512-04 oki semiconductor ml70512 29/29 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the act ual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual prop erty right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this docu ment are intended for use in genera l electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traf fic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2003 oki electric industry co., ltd.

▲Up To Search▲

Price & Availability of ML70512HB

	To Download ML70512HB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .